Semiconductor

Fab Tool Capacity

Situation

Wafer starts pass through lithography, etch/deposition, metrology, and probe/test before becoming qualified output. Each stage can be the bottleneck, and relieving one exposes the next. Budget alone doesn't help when the binding limit is tool availability.

Decision

Which tool family caps qualified wafers this month, and what becomes active if that constraint is relieved?

How we modeled it

The model is a sequential fab flow from wafer starts to qualified wafers. Stage edges carry wafer volume with yield, cost, and carbon rates. Capacity constraints sit on lithography, metrology, and probe/test; the solve maximizes qualified wafers and ranks the active tool limits.

What the model shows

First constraint to relieve+1 lithography shift

Current good output~9.3k wafers/month

Next limit after reliefMetrology becomes binding

Active limits

Lithography fully loaded
Metrology near limit

What this shows

Lithography is the current limit. Once scanner capacity opens, metrology becomes the next governing limit — not budget.

Adding budget alone does not raise wafer output while scanner capacity is fixed.

One lithography shift raises output, then inspection capacity starts to matter.

Capital requests should be sequenced: scanner relief first, then metrology coverage.

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