Factory, semiconductor, space, and aviation programs where capacity and windows decide output.
Which tool constraint limits output, and what becomes the next limit after it is relieved?
Wafer starts pass through lithography, etch/deposition, metrology, and probe/test before becoming qualified output. Each stage can be the bottleneck, and relieving one exposes the next. Budget alone doesn't help when the binding limit is tool availability.
SSPLAX